CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge

ABSTRACT

A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of semiconductor dynamic memories.

2. Prior Art

Metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) dynamicrandom-access memories (DRAMs) continue to increase in density from, forexample, the 1K memories of the late 1960's to the currently used 64Kmemories of today. The described invention is realized in a 256K CMOSmemory, although the inventive concepts described may be utilized inother size memories.

In DRAMS, typically memory cells each of which include a singletransistor and capacitor, are coupled to bit lines. Pairs of bit linesextend from a latch-like sense amplifier. Dummy cells, restore circuits,and architecture employing folded bit lines are commonly used in currentDRAMs.

The capacity of an MOS DRAM can, of course, be increased by employingmore memory cells. But unless higher density fabrication is used, thatis, smaller cells, etc., the higher capacity memories are not suited forhigh volume production because the increased substrate area decreasesyields. There is, thus, always the continuing goal to shrink the size ofthe memory cells. However, as the cells are made smaller, they storeless charge and it becomes increasingly difficult to sense the binarystate stored in the cells. It is easier to sense a smaller cell if thebit line capacitance is reduced and this can be achieved with fewercells on the bit lines allowing them to be shortened. On the other hand,where greater array effeciency is sought, it is helpful if more cellsare placed along each of the bit lines. Using shorter bit lines requiremore sense amplifiers, consequently, some of the increased densitygained by using smaller cells with shorter bit lines can be lost becauseof the additional sense amplifiers and related peripheral circuit (e.g.,decoders).

One prior art suggestion, although not commercialized, is to multiplexpairs of bit lines to a single sense amplifier. This technique, intheory, permits use of the shortened bit lines without requiringadditional sense amplifiers. The present invention employs thistechnique, but not in the manner used in the prior art. For instance,with the present invention, as will be seen, there is a decoupling ofthe bit lines from the sense amplifier when sensing occurs.

In some prior art DRAMs, bit lines are precharged to the full powersupply potential, for example, five volts. In others, the bit lines arecharged to a reference potential such as half the power supplypotential. These precharging techniques are used both with and withoutdummy cells. An obvious advantage to charging to one-half the powersupply potential is that the memory consumes less power. However, thereare a number of problems with this system. In one case, the bit linesare precharged during an inactive cycle. The power supply potential canvary between the time of the precharging and the actual sensing and thisvariation causes difficulty in sensing. Another problem with prechargingthe bit lines to half the power supply potential is that poorperformance results when the power supply potential is low. With thedescribed invention, the bit lines are charged to half the power supplypotential in a unique way and in combination with the multiplexingmentioned above. Not only is less power consumed, but also the peakcurrents are reduced with the present invention.

For recent discussions of DRAM technology, see (1) "A 90NS 256K×1B DRAMWith Double Level AL Technology", ISSCC Digest of Technical Papers pages226-227, Feb. 1983, by Fujii, T. et al; (2) "A 64 Kb CMOS RAM", ISSCCDigest of Technical Papers pages 258,259, Feb. 1982, by Konishi, S. etal, (3) "A 70NS High Density CMOS DRAM", ISSCC Digest of TechnicalPapers pages 56-57, Feb. 1983, by Chwang, R. et al; (4) "A 100 ns 5 VOnly 64K×1 MOS Dynamic RAM", IEEE Journal of Solid-State Circuits pp.839-845, Vol. SC-15, No. 5. Oct. 1980 by Chan, J. et al; and (5) "A5V-Only 64K Dynamic RAM Based on High S/N Design", IEEE Journal ofSolid-State Circuits p. 846, Vol. SC-15, No. 5, Oct. 1980 by Masuda, H.et al.

SUMMARY OF THE INVENTION

A metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) isdescribed. The memory includes a first and a second plurality of memorycells associated with a sense amplifier. A first pair of bit lines arecoupled to the first cells and a second pair of bit lines are coupled tothe second cells. A first switching means permits selective coupling ofthe first pair of the bit lines to the sense amplifier and a secondswitching means permits the selective coupling of the second pair of bitlines to the sense amplifier. Precharging means and a restore circuitare also coupled to each pair of bit lines. One of the first or secondpair of bit lines is coupled through its respective switching means tothe sense amplifier when a memory cell is selected along that pair oflines. The switching means decouples the selected pair of bit lines fromthe sense amplifier when the sense amplifier begins to sense the datafrom the memory cell.

In the currently preferred architecture, the input/output lines in thememory array are coupled to only one pair of the bit lines. The firstand second switching means are used to transfer data from one pair ofbit lines to the other to allow the coupling of data to the input/outputlines.

Another unique aspect of the present invention is that the restorecircuits are separately activated for each pair of bit lines and aredeactivated during writing. Other aspects of the present invention areset forth in the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of the invented memory used to describe thegeneral architecture.

FIG. 2 is an electrical schematic of the presently preferred memorycell, bit lines, sense amplifier, restore circuits, multiplexing meansand interconnection of the bit lines to the input/output lines.

FIG. 3 are timing diagrams used to describe the operation of the circuitof FIG. 2.

FIG. 4 illustrates the sense amplifier of FIG. 2 redrawn for purposes ofexplanation.

FIG. 5 is a diagram used to describe potential levels in the circuit ofFIG. 4.

FIG. 6 are waveforms used to describe current peaks with the inventedmemory.

DETAILED DESCRIPTION OF THE INVENTION

A metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) isdescribed. In the following description, numerous specific details areset forth such as specific arrays, number of cells, etc. It will beobvious to one skilled in the art that the present invention may bepracticed without these specific details. In other instances, well-knowncircuits associated with DRAMs such as decoders, etc., are notillustrated in order not to unnecessarily obscure the present invention.

OVERVIEW OF PREFERRED EMBODIMENT

In the currently preferred embodiment, the DRAM is fabricated employingCMOS technology. In particular, the array is fabricated in an n-wellusing double polycrystalline silicon (polysilicon) technology. Then-well/substrate junction is reverse biased and acts as a minoritycarrier barrier which reduces soft errors induced by alpha particles.The overall structure of the cell is shown in copending application,entitled "CMOS DRAM", Ser. No. 470,454, filed Feb. 28, 1983, andassigned to the assignee of the present invention. The on chip powerdistribution for the disclosed memory is described in copendingapplication Ser. No. 581,285, filed Feb. 17, 1984, entitled "POWERDISTRIBUTION FOR CMOS CHIP", and assigned to the assignee of the presentapplication.

In the currently preferred embodiment, the memory is organized as a256K×1 memory. Gate oxide thicknesses (second layer of polysilicon) of250 A are used. The cells have an area of approximately 70 μm² with astorage capacitance of approximately 55 fF. The word line drivers employa negative "boosted" potential which yields an average cell storedcharge of approximately 275 fC. The bit line to cell capacitance ratiois approximately 12-to-1 providing a 190 mV signal for sensing over awide operating range. The memory operates from a five volt potential anddraws an average current of 45 mA and a standby current of 1 mA. A 256cycle refresh arrangement is used at intervals of 4 mS. The substrate onwhich the entire memory is fabricated includes four redundant rows andcolumns.

Access times of less than 100 ns. are obtained with row accessing. Thememory employs static column circuits, thus permitting a faster"Ripplemode" (a static column mode) access where 512 bits can beaccessed with an access time of approximately 40 nS. per bit and with areduced active current of approximately 25 mA.

ARCHITECTURE OF PREFERRED EMBODIMENT

The 256K×1 organization is realized in the presently preferredembodiment with 16K arrays 10 as shown in FIG. 2. The arrays 10 arepaired and each pair is separated by a row of sense amplifiers 14. Therestore circuits 16 are formed in rows generally parallel to the senseamplifiers at the outer edges of each pair of arrays 10. The columndecoders and data input/output lines are formed in the elongated centralportion 12 of the memory. All data transferred into and from the arraysoccurs through these centrally disposed input/output lines. The outerarrays communicate with the input/output lines through the bit lines ofthe inner arrays as will be described in detail in conjunction with FIG.2.

The row decoders and word line drivers 18 are formed in two horizontalbands. Dual row decoders are used in these bands. The peripheralcircuits, for the most part, are located in the regions 20. Theseinclude the input/output buffering for data, the buffering for addressesand timing signals such as the standard RAS/and CAS/ signals. As iscommonly done, these buffers provide TTL to MOS signal level shifting.

SENSE AMPLIFIER MULTIPLEXING AND RESTORE CIRCUITS

In FIG. 2, two pairs of bit lines, lines 23 and 24, and lines 25 and 26,are selectively coupled to the sense amplifier 30 through transistors 33and 32, respectively. The bit lines 23 and 24 are connected to thecomplementary input/output lines 40 and 41 through transistors 43. Thesetransistors are selected by the column decoders. This technique ispopularly known as multiplexing. For purposes of explanation, the bitlines 23 and 24 are referred to as the inside bit lines (BLI and BLI/)and the bit lines 25 and 26 as the outside bit lines (BLO and BLO/). Thedesignation inside and outside represents the bit line pairs' positionrelative to the input/output lines and sense amplifier 30. (Note thedesignation "left" and "right" may create ambiguities since the left andright lines would be reversed for the two pairs of bit lines extendingto the other side of the input/output lines 40 and 41, shown as lines 54and 55.) The sense amplifier 30 includes a pair of cross coupled p-typetransistors and four capacitors formed from p-channel transistor-likestructures. The amplifier receives a sense amplifier strobe (SAS) signalas is commonly used with DRAM sense amplifiers. The operation of thesense amplifier is discussed in detail in conjunction with FIG. 4.

A plurality of cells is connected to each of the bit lines, each cellcomprises a transistor such as transistor 36 and a storage capacitorsuch as capacitor 37. Word lines in the array select a single capacitorfor coupling to one of the bit lines (of one pair) for reading, writingor refreshing. Note no dummy cells are employed along the bit lines.

Transistors 45 and 46 receive the precharge signal and provide forprecharging of the bit lines. In typical operation, after restoration,one bit line is at the full power supply potential (five volts) and theother at ground. Thus, lines 24 and 25 may be at five volts and lines 23and 26 at ground. The precharging signal causes transistors 45 and 46 toconduct, the charge on the bit line pairs is divided and the bit linesare brought to approximately half the power supply potential, forinstance, 21/2 volts if the power supply potential is a full five volts.Since the bit lines are only changed to 1/2 the supply potential theactive power is reduced by approximately a factor of 2. During thisprecharging, transistors 32 and 33 conduct, assuring that the nodeswithin the sense amplifier are also precharged to this one half V_(CC)potential. (In actuality, the bit lines are above 50% of the powersupply potential (e.g., at 55%). There is some inherent bootstrappingwhich occurs from the restore circuits and also the capacitanceassociated with the junctions is non-linear (e.g., function of voltage).This variation from the 50% figure is process dependent.)

A restore circuit 48 is coupled to the ends of the bit lines 25 and 26and similarly, a restore circuit 49 is coupled to the ends of the bitlines 23 and 24. Each of the restore circuits comprises a pair of crosscoupled n-type transistors. The restore circuit 48 includes transistor50 which couples the cross coupled transistors to ground. Similarly, therestore circuit 49 includes transistor 51 which couples the pair ofcross coupled transistors in circuit 49 to ground. As will be describedin detail, transistors 50 and 51 permit the restore circuits 48 and 49to be separately activated. This distributes the current consumed forrestoring the bit lines into separate periods, thus limiting the peakcurrent. Also, the waveforms used to activate the transistors 50 and 51cause these transistors to conduct gradually, further reducing currentpeaks.

GENERAL OPERATION OF THE CIRCUIT OF FIG. 2

Before referring to the detailed timing diagram, it will be helpful tohave a general understanding of the operation of the circuit of FIG. 2.The circuit operates differently depending upon whether data is beingread from the inside bit lines or outside bit lines.

Assume first that data is to be read from one of the outside bit lines,for example, from the cell comprising transistor 36 and capacitor 37.Initially, both transistor pairs 32 and 33 conduct, and the prechargingtransistors 45 and 46 also conduct. This causes the sense amplifiernodes and both pairs of bit lines to be held at the same potential,approximately 1/2 V_(CC). Next, transistors 33 and the prechargingtransistors 45 and 46 are turned off. The word line is then selected,causing transistor 36 to conduct and line 25 to be either additionallycharged, or the charge on the line is reduced. (Capacitor 37 stores afull potential (e.g., 5 V or 0 V). An imbalance is caused by the chargefrom capacitor 37 on the metal bit line 25 and the nodes of the senseamplifier 30. Now transistors 32 are turned off and sensing within thesense amplifier 30 occurs. Importantly, this sensing occurs with neitherpair of bit lines being connected to the sense amplifier. After sensingoccurs, transistors 33 conduct. The amplified data from the capacitor 37is thus transferred onto the inside bit lines where it can betransferred to the I/O lines 40 and 41. (The specific timing isdiscussed later for these events.) A restore signal is applied totransistor 51 to restore the inside bit lines. Transistors 32 are alsocaused to conduct again so that the data sensed by the sense amplifier30 is transferred onto the outside bit lines. The outside restorecircuit 48 is activated by the application of a signal to transistor 50restoring the outside bit lines, thereby returning capacitor 37 to itsoriginal state.

Therefore, when data is sensed on an outside bit line, it is firsttransferred onto an inside bit line for coupling to the input/outputlines. The inside bit lines are restored first, followed by therestoration of the outside bit lines.

Assume now that data is to be sensed along the inside bit line 24. Onceagain, initally both transistors 32 and 33 are on, and when thetransistors 45 and 46 conduct, all the bit lines and the nodes of theamplifier 30 are brought to approximately 1/2 V_(CC). After theprecharge signal goes low, transistors 32 are turned off and the wordline is activated, causing charge to flow onto or from the bit line 24.Then, transistors 33 are turned off and sensing occurs within theamplifier 30 by application of the (SAS). When transistors 33 are againturned on, the data is transferred onto lines 40 and 41 as transistors43 conduct (after restoring the potential on these lines.) The insidebit lines are restored first. Later, transistors 32 are also permittedto conduct, allowing the outside restore circuit 48 to operate as partof precharge cycle.

As was the case with sensing from outside bit lines, the inside bitlines are isolated from the sense amplifier before data from one ofthese lines is sensed by the sense amplifier. Similarly, one pair of bitlines are restored at a different time than the other pair of bit linesto assure that the current peaks are reduced.

As is apparent from FIG. 2, the sense amplifier and cells are allp-channel devices. The cells are fabricated in n-wells spaced-apart fromthe wells containing the sense amplifiers. The restore circuits andcolumn select transistors are n-channel transistors and are fabricatedoutside the n-well, in the p-type substrate. (The n-well itself isconnected to the positive power supply potential.) By way of example,the full power supply potential of V_(CC) is placed across capacitor 37assuming that the circuit 48 is set to charge capacitor 37. The wordlines are bootstrapped (driven negatively approximately 3 volts belowground potential) to assure complete transfer of charge onto and fromcapacitor 37 and like capacitors. A full V_(CC) potential is applied toone bit line while the other is connected to ground during restoring.(Full V_(CC) is obtained from the SAS signal and ground from circuits 48and 49.)

Decoders are employed to examine each address and determine which onesof the transistors 32 and 33 are to remain coupled to the senseamplifier after the precharge and prior to the sensing. Such decodersare well-known and may be similar to those used for activating dummyloads, or dummy cells, in prior art DRAMs.

It should be noted that since the bit lines are charged to approximately1/2 V_(CC), there is no difficulty transferring charge over transistors32 and 33.

WAVEFORMS OF FIG. 3

Referring to FIG. 3, at the beginning of the active cycle, the rowaddress strobe signal (RAS/) as shown by waveform 80, drops inpotential. This initiates an active memory cycle. Following the RAS/signal's drop in potential, precharging occurs. This is indicated by thewaveform 81. Unlike prior art memories, precharging occurs during theactive cycle. This does not add to access time since decoding ofaddresses, etc. is accomplished during this precharging. This assuresthat the precharge potential is referenced to the current V_(CC). Notethat the sense amplifier's strobe signal is on until the prechargingoccurs and then drops as shown by waveform 82.

In FIG. 3, the waveform coupled to the gates of transistors 32 is shownas T1 and for transistors 33 as T2. Waveforms 83 and 84 are for sensingdata on an outside bit lines. Initially both sets of transistors 32 and33 are conducting then transistors 33 are turned off, followed bytransistors 32. Transistors 33 are turned on after sensing occurs asindicated by the line 86, and sometime later, transistors 32 are thenturned on.

The word line potential drops to approximately -3 volts as shown bywaveform 85 to fully transfer charge from a cell. For the outside bitline sensing shown, the potentials on these bit lines are shown bywaveforms 87. Initially, one line is at five volts and the other atground, then during the precharge period, both are brought to one-halfV_(CC). One line changes potential slightly when the word line isactivated, the other remains at one-half V_(CC).

The potentials on the sense amplifier nodes are shown by waveforms 88.Once again, one of these potentials are initially at V_(CC) and theother at ground. After precharge, the nodes are equalized and there is aslight change on one mode before sensing begins. Sensing occurs when theSAS signal rises in potential. Waveforms 89 represent the potentials onthe inside bit lines. Note that as previously discussed, even though acell is selected on one of these bit lines, they are not restored untilafter the active cycle as indicated by the rise in potential in waveform91, the restore signal for the outside restore circuit. Waveform 90illustrates that the inside restore occurs first and line 92 shows theseparation in time between the inside and outside restoring. The columnselection signal rises in potential as shown by waveform 93 shortlyafter the inside restore signal rises in potential. Thus, thedifferential on the inside bit lines will be a full V_(CC). The data onthe I/O lines is indicated by waveforms 94; and, waveforms 95illustrates when the data is valid.

All of the above waveforms may be generated with well-known circuitscommonly used in DRAMs. For this reason, the timing circuits have notbeen shown.

The timing signals for sensing on inside bit lines are substantially thesame as those of FIG. 3 with the differences discussed above,particularly the timing for transistors 32 and 33.

In the presently preferred embodiment, during a write cycle, no restorecircuits are used. They are temporarily deactivated. The bit lines aredriven directly from the input/output lines shown in FIG. 2. This speedsup the writing cycles. In the prior art, the restore circuits areactivated since there is no way of decoupling them. With the presentinvention, these circuits can be selectively activated as they areduring a read/restore cycle and also, both circuits can be leftdeactivated as they are during a write cycle.

SENSE AMPLIFIER OF FIG. 4

The sense amplifier of FIG. 2 has been redrawn in FIG. 4 so that boththe true and complementary bit lines (both inside and outside) are shownon the same level. Capacitors 61 and 62 are coupled between the nodes 67and 68 and similarly, capacitors 63 and 64 are coupled between thesenodes. The p-channel transistor 50 is coupled between nodes 67 and thenode 57 (source of the SAS signal). Its gate is coupled to node 68.Transistor 60 has its gate coupled to node 67, one of its terminals iscoupled to node 68 and the other terminal to node 57.

For reasons that will be explained, capacitors 61 (C₂) and 64 (C₂) havethe same capacitance and capacitors 62 (C₁) and 63 (C₁) also have thesame capacitance. The capacitance of C₂ is slightly larger than thecapacitance of C₁, by approximately 5% in the presently preferredembodiment (the specific difference of 5% is not crucial to the presentinvention).

Ideally, when sensing either a binary one or a binary zero, the swing onthe bit line should be the same, although in opposite directions. Thereare a number of effects which prevent this ideal condition. Forinstance, when the negative potential is applied to the word line, thecapacitive coupling between the word line and bit line (e.g., gate oftransistor 36 and line 25 of FIG. 2) brings the bit line more negative.Also, the bit line capacitance is not linear with respect to voltage fora number of reasons such as the parasitic capacitance associated withthe source and drain regions of transistors 32 and 33. Another effectpreviously discussed is that the actual precharge potential on the bitlines is not precisely V_(CC) /2. The capacitance of the cellsthemselves is also not linear with respect to voltage. There are othereffects which cause deviation from the ideal condition and which make itdifficult to sense data particlarly as the cell size is reduced.

Briefly in FIG. 5, line 71 represents the ideal voltage on the bit linesafter precharging. The swing of this line in the more negative directionat section 72 indicates the pull on one of the bit lines which occurswhen the word line is activated. (The charge from the cell is beingignored for this explanation.)

The capacitors 61 through 64 provide compensation for theabove-described effects among others. From ordinary decoding of theaddress signals, it can be determined if a cell is to be accessed oneither a true bit line or a complementary bit line. Assume that a cellalong line 25 is to be accessed. A potential is applied to line 74 (notline 75). Since capacitor C2 is larger than capacitor C1, line 67 isdriven less negatively providing compensation for the above-describedeffects. This is shown by 73 in FIG. 5. Similarly, if a cell is selectedalong the true bit lines 23 or 26, the signal is applied to line 75causing line 68 to be higher in potential than the other bit lineproviding like compensation.

The capacitors discussed above permit more precise adjustment than canbe obtained from using dummy cells, especially where smaller cells areemployed. Additionally they provide a D.C. offset which improves gainand compensation in both directions.

REDUCTION IN CURRENT PEAKS

In FIG. 6, three waveforms are shown to illustrate the distribution ofcurrent that occurs since half the array is restored at one time and theother half at another time. Once again, the RAS/ signal is showndropping in potential; this initiates an active cycle. During the activecycle, and before the data is valid, restoration of half the bit linesoccurs. Later, and in fact, during a precharge cycle (after RAS/ risesin potential) the other half of the bit lines are restored. This reducespeak currents and distributes these large current demands into twoseparate periods. Also, while not shown in detail in FIG. 3, the signalsused to activate the restore circuits are ramped. This further reducesthe peak current during both restore cycles. These techniques reducepeak currents without adding to access time.

Thus, a CMOS dram has been described which employs two pairs of bitlines multiplexed onto a single sense amplifier. No dummy cells areemployed in the described memory. The bit lines are charged to one-halfthe voltage supply potential. Peak currents are reduced since half thebit lines are restored during one period of time and the other half arerestored during another period of time.

We claim:
 1. A metal-oxide-semiconductor (MOS), dynamic random-accessmemory (DRAM) comprising:a first and a second plurality of memory cells;a sense amplifier; a first pair of bit lines, coupled to said firstcells; a first switching means for selectively coupling said first pairof bit lines to said sense amplifier, said first switching means beingcoupled to said first bit lines and said sense amplifier; a second pairof bit lines, coupled to said second cells; a second switching means forselectively coupling said second pair of bit lines to said senseamplifier, said second switching means being coupled to said second bitlines and said sense amplifier; precharging means for precharging saidfirst and second pairs of bit lines, said precharging means for couplingsaid pairs of bit lines together to equalize the potential on said bitlines; one of said first and second pairs of bit lines being coupled tosaid sense amplifier by one of said first and second switching meanswhen one of said memory cells on said one pair of bit lines is selected;said one switching means decoupling said one pair of bit lines fromsense amplifier as said sense amplifier senses data from said one memorycell; whereby effective sensing of data in said memory cells is achievedwithout dummy cells where said bit line pairs are selectively coupled tosaid sense amplifier.
 2. The DRAM defined by claim 1 including first andsecond restoring circuits coupled to said first and second pairs of bitlines, respectively.
 3. The DRAM defined by claim 2 wherein said secondpair of bit lines are selectively coupled to a pair of input/outputlines.
 4. The DRAM defined by claim 3 wherein said first and secondrestoring circuits are separately activated.
 5. The DRAM defined byclaim 4 wherein when data is being sensed from one of said first cells,said second switching means decouples said second pair of bit lines fromsaid sense amplifier and after said one memory cell is selected, saidfirst switching means decouples said first pair of bit lines from saidsense amplifier.
 6. The DRAM defined by claims 4 or 5 wherein when datais being sensed from one of said second cells, said first switchingmeans first decouples said first pair of bit lines from said senseamplifier, and subsequently said second switching means decouples saidsecond pair of bit lines from said sense amplifier after said one ofsaid second cells has been selected.
 7. The DRAM defined by claim 6wherein said precharging means for precharging said pairs of bit linestogether to one-half the power potential used by said DRAM.
 8. The DRAMdefined by claim 3 wherein said sense amplifier includes imbalancedcapacitors and wherein a signal is applied to said imbalanced capacitorsto adjust potentials on one of said pairs of bit lines to compensate fora parasitic change in potential on one of said bit lines which occurswhen a word line is activated.
 9. The DRAM defined by claims 3 or 8wherein said sense amplifier is fabricated from transistors of a firstconductivity type and said restoring circuits are fabricated fromtransistors of a second conductivity type.
 10. The DRAM defined by claim9 wherein said first conductivity type is p-type and said secondconductivity type is n-type.
 11. A metal-oxide-semiconductor (MOS)dynamic, random-access memory (DRAM) comprising:first and second pairsof bit lines; a plurality of memory cells coupled to said bit lines; asense amplifier; multiplexing means for selectively coupling one of saidfirst and second pairs of bit lines to said sense amplifier, saidmultiplexing means coupled to said first and second pairs of bit linesand said sense amplifier; first and second restoring means forselectively restoring potentials on said first and second pairs of bitlines, respectively during a read/restore cycle, said restoring meanscoupled to said pairs of bit lines; said first and second restoringmeans being separately activated at different time sequence forrestoring potentials on said first and second pairs of bit lines atdifferent times; whereby current peaks for said DRAM are reduced. 12.The DRAM defined by claim 11 wherein both said restoring means aredeselected for writing into said DRAM.
 13. The DRAM defined by claim 11wherein said sense amplifier is fabricated from devices of a firstconductivity type and said restoring means are fabricated fromtransistors of a second conductivity type.
 14. The DRAM defined byclaims 11 or 13 including precharging means to precharge said pairs ofbit lines to one-half the power supply potential used by said DRAM. 15.The DRAM defined by claim 14 wherein said first and second restoringmeans causes one line from said first pair of bit lines and one linefrom said second pair of bit lines to be charged to full power supplypotential and the other line of said first and second pairs of bit linesto be coupled to ground and wherein said precharging means couples saidlines together.
 16. The memory defined by claim 13 wherein said firstconductivity type is p-type and second type is n-type.
 17. The DRAMdefined by claim 11 wherein said second pair of bit lines areselectively coupled to complementary input/output lines.
 18. The DRAMdefined by claim 11 wherein said sense amplifier includes pairs ofimbalanced capacitors which receive signals during sensing, saidimbalanced capacitors providing compensation for parisitic coupling ofsignals bit lines.
 19. A metal-oxide-semiconductor (MOS) dynamic,random-access memory (DRAM) comprising:a first pair of bit lines; aplurality of memory cells coupled to said first pair of bit lines; asense amplifier coupled to said first pair of bit lines, said senseamplifier including a pair of imbalanced capacitors which receivesignals during sensing, said imbalanced capacitors providingcompensation for parasitic coupling of signals to said first pair of bitlines; restoring means for selectively restoring potentials on saidfirst pair of bit lines during a read/store cycle, coupled to said firstpair of bit lines; and precharging means for precharging said bit linesto approximately 1/2 the power supply potential used by said DRAM;whereby improved sensing of signals on said first pair of bit linesoccurs.
 20. The DRAM defined by claim 19 including a second pair of bitlines and multiplexing means for selectively coupling one of said firstand second pairs of bit lines to said sense amplifier, said multiplexingmeans coupled to said first and second pairs of bit lines and said senseamplifier.
 21. A metal-oxide-semiconductor (MOS) dynamic, random-accessmemory (DRAM) comprising:a first pair of bit lines; a plurality ofmemory cells coupled to said first pair of bit lines; a sense amplifiercoupled to said first pair of bit lines; restoration means forselectively restoring potentials on said first pair of bit lines duringa read/store cycle, said restoration means coupled to said bit lines,said restoration means applying a potential approximately equal to thepower supply potential to one of said lines while coupling the other ofsaid lines to ground potential; precharge means for precharging saidpair of bit lines to a potential approximately equal to one-half saidpower supply potential, said precharge means coupling said first pair ofbit lines together during an active memory cycle, whereby a DRAMconsuming less power is achieved.
 22. The DRAM defined by claim 21wherein said sense amplifier includes two pairs of imbalanced capacitorscoupled to said sense amplifier and coupled to receive a signal duringsensing, such that only one of said pairs of capacitors receive saidsignal during sensing to provide compensation for parasitic coupling tosaid bit lines.
 23. The DRAM defined by claim 21 or claim 22 including asecond pair of bit lines having a plurality of memory cells coupled tosaid second pair of bit lines, and multiplexing means for selectivelycoupling one of said first and second pair of bit lines to said senseamplifier, said multiplexing means coupled to said first and secondpairs of bit lines and said sense amplifier.